cocotb_activehdl_sim

load("@rules_cocotb//cocotb:cocotb_activehdl_sim.bzl", "cocotb_activehdl_sim")

cocotb_activehdl_sim(name, env, vcom, vlib, vlog, vsimsa)

A simulator configuration for running Aldec Active-HDL simulations in cocotb tests.

Infrastructure only. Active-HDL is commercial, with no BCR module and no redistributable binary; rules_cocotb cannot validate this rule in CI. Wire it up downstream by pointing the binary attrs at your own install and registering a cocotb_toolchain that routes sim = "activehdl" through this rule. Cocotb's runner handles the actual build/sim via Runner.build / Runner.test.

Downstream wiring

The pattern matches cocotb_riviera_sim — wrap the installed vlib, vlog, vcom, and vsimsa binaries via a local repository, then:

load("@rules_cocotb//cocotb:cocotb_activehdl_sim.bzl", "cocotb_activehdl_sim")
load("@rules_cocotb//cocotb:cocotb_toolchain.bzl", "cocotb_toolchain")

cocotb_activehdl_sim(
    name = "cocotb_activehdl",
    vlib = "@activehdl//:vlib",
    vlog = "@activehdl//:vlog",
    vcom = "@activehdl//:vcom",
    vsimsa = "@activehdl//:vsimsa",
)

cocotb_toolchain(
    name = "my_cocotb_toolchain",
    cocotb = "//path/to:cocotb_py_library",
    simulators = {":cocotb_activehdl": "activehdl"},
)

Active-HDL accepts both Verilog/SystemVerilog (VerilogInfo) and VHDL (VhdlInfo) modules.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
env	Environment variables to set when the cocotb runner invokes this simulator at test time (license-server pointers, install root vars, …). Precedence: toolchain `env` < sim `env` < rule-level `cocotb_test(env = ...)`.	Dictionary: String -> String	optional	`{}`
vcom	The `vcom` VHDL compiler binary.	Label	required
vlib	The `vlib` library manager binary.	Label	required
vlog	The `vlog` Verilog compiler binary.	Label	required
vsimsa	The `vsimsa` batch simulation runner binary.	Label	required

rules_cocotb

Rules

cocotb_activehdl_sim

Status

Downstream wiring