cocotb_icarus_sim

Rules

cocotb_icarus_sim

load("@rules_cocotb//cocotb:cocotb_icarus_sim.bzl", "cocotb_icarus_sim")

cocotb_icarus_sim(name, env, iverilog, ivl_base, ivl_files, vvp)

A simulator configuration for running Icarus Verilog binaries in cocotb tests.

Status

Fully functional. Sourced from the BCR iverilog module (bazel_dep(name = "iverilog", version = "13.0.bcr.1")). The default toolchain wires iverilog, vvp, and the IVL backend components. Exercised end-to-end by the in-tree adder_icarus_test.

Notes

The iverilog driver locates its backend components (ivl, vvp.tgt, system.vpi, etc.) via the IVL_BASE environment variable. For the BCR iverilog module, the components are exposed as individual labels; this rule's ivl_files attribute maps each label to its expected filename and assembles them into a directory for IVL_BASE.

Icarus only supports Verilog/SystemVerilog (VerilogInfo); pair it with a verilog_library target as the module.

ATTRIBUTES

NameDescriptionTypeMandatoryDefault
nameA unique name for this target.Namerequired
envEnvironment variables to set when the cocotb runner invokes this simulator at test time (license-server pointers, install root vars, …). Precedence: toolchain env < sim env < rule-level cocotb_test(env = ...).Dictionary: String -> Stringoptional{}
iverilogThe iverilog compiler binary.Labelrequired
ivl_baseA pre-assembled IVL_BASE directory (e.g. a filegroup wrapping /usr/lib/ivl for a system iverilog). The rule sets IVL_BASE to this directory's path during compilation. Mutually exclusive with ivl_files.LabeloptionalNone
ivl_filesComponents to assemble into an IVL_BASE directory. Maps source labels to destination filenames (e.g. {"@iverilog//:ivl": "ivl", "@iverilog//tgt-vvp:vvp_tgt": "vvp.tgt"}). Designed for the BCR iverilog module's per-component layout — for an IVL_BASE directory that already exists on disk, use ivl_base instead. Mutually exclusive with ivl_base.Dictionary: Label -> Stringoptional{}
vvpThe vvp simulation runner binary.Labelrequired