cocotb_test
Rules
cocotb_test
load("@rules_cocotb//cocotb:cocotb_test.bzl", "cocotb_test")
cocotb_test(name, deps, srcs, data, env, module, params, precompiled_libs, sim, sim_opts)
Run a test using cocotb on a given Verilog/VHDL module.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| deps | Python dependencies required by the test sources. | List of labels | optional | [] |
| srcs | Sources containing the test code to run. | List of labels | required | |
| data | Additional runtime data used by the test. | List of labels | optional | [] |
| env | Environment variables to set for the test. | Dictionary: String -> String | optional | {} |
| module | The Verilog/VHDL module to test. | Label | required | |
| params | Verilog parameters or VHDL generics. | List of strings | optional | [] |
| precompiled_libs | Precompiled simulator library sets to link before the test's own compile step. Each target must produce a CocotbPrecompiledLibraryInfo whose format matches this test's resolved simulator's format family (analysis-time check). At runtime the per-format runner patch in cocotb_process_wrapper emits the vendor's link directive (vmap -link for Aldec, -modelsimini for Mentor, etc.) so DUT wrappers that reference libraries inside the precompiled set (e.g. Xilinx's xil_defaultlib) resolve. | List of labels | optional | [] |
| sim | The name of the simulator to use. Must match a key in the cocotb_toolchain's simulators dict. | String | optional | "" |
| sim_opts | Additional command line arguments to pass only to the simulator during code-generation. | List of strings | optional | [] |