Public entry point for riviera_library.
Rules
riviera_library
load("@rules_riviera//riviera:riviera_library.bzl", "riviera_library")
riviera_library(name, deps, srcs, acom_opts, alog_opts, exec_requirements, jobs, library_name,
link_libraries)
Compile the full transitive HDL DAG into ONE self-contained Aldec Riviera library.
deps takes verilog_library / vhdl_library targets (anything
providing VerilogInfo or VhdlInfo). The rule walks the whole
reachable source graph — own srcs + hdrs, transitive .deps, and
cross-language .vhdl_deps / .verilog_deps, through any number of
language boundaries — and compiles it in one alib/alog/acom
invocation via a generated vsimsa .do script. includes become
+incdir+ paths; data files are compile inputs and are forwarded as
runfiles to riviera_sim_test. Output is one TreeArtifact directory; riviera_sim_test
vmaps it by the logical library name.
srcs is an optional escape hatch for HDL files that only make sense
inside this Riviera library (a Riviera-specific stub, a compile-time
wrapper) and don't warrant their own HDL-library target.
Runs through //tools/riviera_wrapper, which isolates vsimsa's HOME,
maps link_libraries, cleans up the session library.cfg, and only
prints the transcript when the compile fails.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| deps | verilog_library / vhdl_library targets; their full transitive source graph is compiled into this library. | List of labels | optional | [] |
| srcs | HDL files compiled directly into this library, after everything from deps. Prefer deps for anything another target might also want. | List of labels | optional | [] |
| acom_opts | Extra flags forwarded to VHDL compilation (acom). | List of strings | optional | [] |
| alog_opts | Extra flags forwarded to Verilog compilation (alog) | List of strings | optional | [] |
| exec_requirements | Extra execution_requirements merged over the toolchain's (resources:<name> for each of its resources, plus requires-network when it sets it). | Dictionary: String -> String | optional | {} |
| jobs | CPU slots to request from Bazel's scheduler. -1 inherits the toolchain's jobs; N > 0 requests N; anything else is no hint. Compiler parallelism flags go in alog_opts / acom_opts. | Integer | optional | -1 |
| library_name | Logical Riviera library name. Defaults to the target's label name. | String | optional | "" |
| link_libraries | Pre-compiled RivieraLibraryInfo targets vmapped before this compile, so library <name>; use <name>.<pkg>.all; clauses resolve. Unlike deps, their sources are not compiled into this library. | List of labels | optional | [] |