verible_diff_test rule

Rules

verible_diff_test

load("@rules_verible//verible:verible_diff_test.bzl", "verible_diff_test")

verible_diff_test(name, file1, file2, mode)

Test rule that runs verible-verilog-diff between two Verilog sources.

By default the comparison uses format mode, which ignores whitespace and compares token texts — useful for verifying that some transformed source still parses to the same tokens as a golden reference. Set mode = "obfuscate" to compare token-text lengths only, the standard recipe for verifying verible-verilog-obfuscate output.

The test exits 0 when the sources are equivalent under the chosen mode, and with the diff binary's non-zero status (1) otherwise; the per-token mismatch report is emitted to the test log.

ATTRIBUTES

NameDescriptionTypeMandatoryDefault
nameA unique name for this target.Namerequired
file1The first Verilog/SystemVerilog source file.Labelrequired
file2The second Verilog/SystemVerilog source file.Labelrequired
modeDiff mode passed to verible-verilog-diff --mode=....Stringoptional"format"