IP packaging rules

Rules

vivado_create_interface_ip

load("@rules_vivado//vivado:ip.bzl", "vivado_create_interface_ip")

vivado_create_interface_ip(name, create_interface_ip_template, description, interface, module,
                           part_number, vendor_display_name)

Package a Vivado interface definition as an IP block. Unlike vivado_create_ip, this does not require a top module.

ATTRIBUTES

NameDescriptionTypeMandatoryDefault
nameA unique name for this target.Namerequired
create_interface_ip_templateThe TCL template for creating interface IP.Labeloptional"@rules_vivado//vivado/private:create_interface_ip.tcl.template"
descriptionDescription for the IP block.Stringoptional""
interfaceThe interface definition to package.Labelrequired
moduleThe verilog_library containing the interface source file(s).LabeloptionalNone
part_numberThe targeted xilinx part.Stringrequired
vendor_display_nameDisplay name for the vendor.Stringoptional""

vivado_create_ip

load("@rules_vivado//vivado:ip.bzl", "vivado_create_ip")

vivado_create_ip(name, create_ip_block_template, encrypt, ip_blocks, ip_library, ip_vendor,
                 ip_version, jobs, keyfile, module, module_top, part_number)

Use vivado to package a module into an IP core

ATTRIBUTES

NameDescriptionTypeMandatoryDefault
nameA unique name for this target.Namerequired
create_ip_block_templateThe create project tcl templateLabeloptional"@rules_vivado//vivado/private:create_ip_block.tcl.template"
encryptEncrypt the sources. Note: This requires a license. See: https://support.xilinx.com/s/article/68071?language=en_USBooleanoptionalFalse
ip_blocksIp blocks to include in this design.List of labelsoptional[]
ip_libraryThe version of this ip core.Stringrequired
ip_vendorThe version of this ip core.Stringrequired
ip_versionThe version of this ip core.Stringrequired
jobsJobs to pass to vivado which defines the amount of parallelism.Integeroptional4
keyfileThe keyfile to use when optionally encryptingLabeloptional"@rules_vivado//vivado/private:xilinx_keyfile.txt"
moduleThe top level build.Labelrequired
module_topThe name of the top level verilog module.Stringrequired
part_numberThe targeted xilinx part.Stringrequired

vivado_interface_definition

load("@rules_vivado//vivado:ip.bzl", "vivado_interface_definition")

vivado_interface_definition(name, src, abstraction_definition_template, bus_definition_template,
                            description, direct_connection, interface_name, interface_setup_template,
                            is_addressable, library, max_masters, max_slaves, parser, vendor, version)

Generate Vivado IP-XACT interface definition files (bus definition and abstraction definition XML).

ATTRIBUTES

NameDescriptionTypeMandatoryDefault
nameA unique name for this target.Namerequired
srcThe SystemVerilog interface source file to parse.Labelrequired
abstraction_definition_templateThe abstraction definition XML template.Labeloptional"@rules_vivado//vivado/private:abstraction_definition.xml.template"
bus_definition_templateThe bus definition XML template.Labeloptional"@rules_vivado//vivado/private:bus_definition.xml.template"
descriptionDescription for the interface.Stringoptional""
direct_connectionWhether direct connections are allowed.BooleanoptionalTrue
interface_nameThe name of the interface (e.g., 'hbm_reader').Stringrequired
interface_setup_templateThe interface setup TCL template.Labeloptional"@rules_vivado//vivado/private:interface_setup.tcl.template"
is_addressableWhether the interface is addressable.BooleanoptionalTrue
libraryThe library VLNV component (e.g., 'interface').Stringoptional"interface"
max_mastersMaximum number of masters.Integeroptional1
max_slavesMaximum number of slaves.Integeroptional1
parserPython parser script (SV -> JSON). Override to customize SV parsing.Labeloptional"@rules_vivado//vivado/private:parse_sv_interface"
vendorThe vendor VLNV component (e.g., 'mycompany.com').Stringrequired
versionThe version VLNV component (e.g., '1.0').Stringoptional"1.0"