vunit_test
Rules
vunit_test
load("@rules_vunit//vunit:vunit_test.bzl", "vunit_test")
vunit_test(name, deps, data, env, module, precompiled_libs, sim, sim_opts)
Run a VUnit test over the given HDL libraries.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| deps | Extra Python dependencies merged into the wrapper's venv. Use this to make helper packages importable from a custom toolchain run.py. | List of labels | optional | [] |
| data | Additional runtime data used by the test. | List of labels | optional | [] |
| env | Environment variables to set for the test. | Dictionary: String -> String | optional | {} |
| module | Root HDL library target whose transitive VhdlInfo/VerilogInfo deps are walked to discover every source the test should compile. Each reachable VhdlInfo contributes its sources under its own library field (fallback "work"). Verilog sources land in the module's own VHDL library when module is a vhdl_library (mixed-language testbench → one shared library by default), otherwise "work". VhdlInfo.deps / VerilogInfo.deps are already transitive depsets, so no aspect or extra walking machinery is involved — the provider IS the DAG. | Label | required | |
| precompiled_libs | Precompiled simulator library sets to link before the test's own compile step. Each target must produce a VUnitPrecompiledLibraryInfo whose simulator field matches this test's resolved sim (analysis-time check). At runtime the per-format runner patch in vunit_process_wrapper emits the vendor's link directive (vmap -link for Aldec, etc.) so HDL that references libraries inside the precompiled set (e.g. Xilinx's xil_defaultlib, unisim) resolves. | List of labels | optional | [] |
| sim | The name of the simulator to use. Must match a key in the vunit_toolchain's simulators dict. | String | optional | "" |
| sim_opts | Additional command line arguments to forward to the simulator via VUnit. | List of strings | optional | [] |