Synthesis-phase rules: vivado_synthesize and vivado_synthesis_optimize.

Rules

vivado_synthesis_optimize
vivado_synthesize

vivado_synthesis_optimize

load("@rules_vivado//vivado:synthesis.bzl", "vivado_synthesis_optimize")

vivado_synthesis_optimize(name, checkpoint, opt_directive, synthesis_optimize_template, threads,
                          with_probes)

Run post-synthesis optimization on a synthesis checkpoint.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
checkpoint	Synthesis checkpoint.	Label	required
opt_directive	The optimization directive.	String	optional	`"Explore"`
synthesis_optimize_template	The synthesis optimization tcl template	Label	optional	`"@rules_vivado//vivado/private:synth_optimize.tcl.template"`
threads	Threads to pass to vivado which defines the amount of parallelism.	Integer	optional	`8`
with_probes	Create debug probes.	Boolean	optional	`False`

vivado_synthesize

load("@rules_vivado//vivado:synthesis.bzl", "vivado_synthesize")

vivado_synthesize(name, create_project_tcl_template, ip_blocks, jobs, module, module_top,
                  part_number, synth_strategy)

Create a Vivado project and run synthesis on it.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
create_project_tcl_template	The create project tcl template	Label	optional	`"@rules_vivado//vivado/private:create_project.tcl.template"`
ip_blocks	Ip blocks to include in this design.	List of labels	optional	`[]`
jobs	Jobs to pass to vivado which defines the amount of parallelism.	Integer	optional	`4`
module	The top level build.	Label	required
module_top	The name of the top level verilog module.	String	required
part_number	The targeted xilinx part.	String	required
synth_strategy	The synthesis strategy to use.	String	optional	`"Vivado Synthesis Defaults"`