vivado_create_project rule: build a Vivado project without synthesizing.
Rules
vivado_create_project
load("@rules_vivado//vivado:project.bzl", "vivado_create_project")
vivado_create_project(name, create_project_tcl_template, ip_blocks, jobs, module, module_top,
part_number)
Create a Vivado project from a verilog_library without running synthesis.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| create_project_tcl_template | The create project tcl template | Label | optional | "@rules_vivado//vivado/private:create_project.tcl.template" |
| ip_blocks | Ip blocks to include in this design. | List of labels | optional | [] |
| jobs | Jobs to pass to vivado which defines the amount of parallelism. | Integer | optional | 4 |
| module | The top level build. | Label | required | |
| module_top | The name of the top level verilog module. | String | required | |
| part_number | The targeted xilinx part. | String | required |