vunit_activehdl_sim
Rules
vunit_activehdl_sim
load("@rules_vunit//vunit:vunit_activehdl_sim.bzl", "vunit_activehdl_sim")
vunit_activehdl_sim(name, env, vcom, vlib, vlog, vsim)
A simulator configuration for running Aldec Active-HDL under VUnit.
Status
Infrastructure only. Active-HDL is commercial, with no BCR module and
no redistributable binary; rules_vunit cannot validate this rule in
CI.
Notes
Active-HDL accepts both Verilog/SystemVerilog (VerilogInfo) and VHDL
(VhdlInfo) modules. Sets VUNIT_SIMULATOR=activehdl.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| env | Environment variables to set when the vunit runner invokes this simulator at test time (license-server pointers, install root vars, …). Precedence: toolchain env < sim env < rule-level vunit_test(env = ...). | Dictionary: String -> String | optional | {} |
| vcom | The vcom VHDL compiler binary. | Label | required | |
| vlib | The vlib library manager binary. | Label | required | |
| vlog | The vlog Verilog/SystemVerilog compiler binary. | Label | required | |
| vsim | The vsim simulator binary. | Label | required |