vunit_riviera_sim

Rules

vunit_riviera_sim

vunit_riviera_sim

load("@rules_vunit//vunit:vunit_riviera_sim.bzl", "vunit_riviera_sim")

vunit_riviera_sim(name, coverage_args, coverage_data_glob, coverage_tool, env, vcom, vlib, vlist,
                  vlog, vmap, vsim, vsimsa)

A simulator configuration for running Aldec Riviera-PRO under VUnit.

Status

Infrastructure only. Riviera-PRO is commercial, with no BCR module and no redistributable binary; rules_vunit cannot validate this rule in CI.

Notes

Riviera-PRO accepts both Verilog/SystemVerilog (VerilogInfo) and VHDL (VhdlInfo) modules. Sets VUNIT_SIMULATOR=rivierapro.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
coverage_args	Template fragments forwarded to `coverage_tool` after the test runs under `bazel coverage`. `{output}` is substituted with `$COVERAGE_OUTPUT_FILE`; `{data_files}` is expanded into one positional arg per file matched by `coverage_data_glob`. Only meaningful when `coverage_tool` is set.	List of strings	optional	`[]`
coverage_data_glob	Shell glob (relative to the VUnit output dir) selecting the raw coverage data files `coverage_tool` consumes. For Riviera-PRO, `**/coverage.acdb` matches every per-testcase ACDB the run produces. Only meaningful when `coverage_tool` is set.	String	optional	`""`
coverage_tool	Optional Riviera coverage post-processor. When set AND the test runs under `bazel coverage` (Bazel populates `$COVERAGE_OUTPUT_FILE`), the rules_vunit process wrapper invokes this binary after the sim exits with the `coverage_args` template (substituting `{output}` and `{data_files}`) so it can translate the merged ACDB into lcov at `$COVERAGE_OUTPUT_FILE`. Leave unset to ship raw ACDBs under the test outputs dir without an lcov roll-up.	Label	optional	`None`
env	Environment variables to set when the vunit runner invokes this simulator at test time (license-server pointers, install root vars, …). Precedence: toolchain `env` < sim `env` < rule-level `vunit_test(env = ...)`.	Dictionary: String -> String	optional	`{}`
vcom	The `vcom` VHDL compiler binary.	Label	required
vlib	The `vlib` library manager binary.	Label	required
vlist	The `vlist` library lister binary. Invoked by `vu.main()` to enumerate compiled units in the library.cfg.	Label	required
vlog	The `vlog` Verilog/SystemVerilog compiler binary.	Label	required
vmap	The `vmap` library-mapping binary. Invoked when external (precompiled) libraries are linked into the test's library.cfg.	Label	required
vsim	The `vsim` simulator binary.	Label	required
vsimsa	The `vsimsa` batch-shell binary. Required: VUnit's `RivieraProInterface.find_prefix_from_path()` rejects a toolchain directory unless BOTH `vsim` AND `vsimsa` resolve in the same dir on PATH. Omitting `vsimsa` produces a confusing `No available simulator detected` error at test time.	Label	required