vunit_questa_sim
Rules
vunit_questa_sim
load("@rules_vunit//vunit:vunit_questa_sim.bzl", "vunit_questa_sim")
vunit_questa_sim(name, env, vcom, vlib, vlog, vsim)
A simulator configuration for running Mentor/Siemens EDA Questa under VUnit.
Functionally identical to vunit_modelsim_sim — VUnit shares one
backend for both products. Use whichever name suits your team's
terminology.
Status
Infrastructure only. Questa is commercial, with no BCR module and no
redistributable binary; rules_vunit cannot validate this rule in CI.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| env | Environment variables to set when the vunit runner invokes this simulator at test time (license-server pointers, install root vars, …). Precedence: toolchain env < sim env < rule-level vunit_test(env = ...). | Dictionary: String -> String | optional | {} |
| vcom | The vcom VHDL compiler binary. | Label | required | |
| vlib | The vlib library manager binary. | Label | required | |
| vlog | The vlog Verilog/SystemVerilog compiler binary. | Label | required | |
| vsim | The vsim simulator binary. | Label | required |