vunit_modelsim_sim
Rules
vunit_modelsim_sim
load("@rules_vunit//vunit:vunit_modelsim_sim.bzl", "vunit_modelsim_sim")
vunit_modelsim_sim(name, env, vcom, vlib, vlog, vsim)
A simulator configuration for running Mentor/Siemens EDA ModelSim under VUnit.
VUnit shares the modelsim backend for both ModelSim and Questa; use
vunit_questa_sim if you prefer that terminology — they wire up the
same VUnit backend.
Status
Infrastructure only. ModelSim is commercial, with no BCR module and no
redistributable binary; rules_vunit cannot validate this rule in CI.
Wire it up downstream by pointing the binary attrs at your own install
and registering a vunit_toolchain that routes sim = "modelsim"
through this rule.
Notes
ModelSim accepts both Verilog/SystemVerilog (VerilogInfo) and VHDL
(VhdlInfo) modules. VUnit drives vlib / vlog / vcom / vsim via
its own runner — the rule just stages sources and surfaces the
binaries on PATH.
ATTRIBUTES
| Name | Description | Type | Mandatory | Default |
|---|---|---|---|---|
| name | A unique name for this target. | Name | required | |
| env | Environment variables to set when the vunit runner invokes this simulator at test time (license-server pointers, install root vars, …). Precedence: toolchain env < sim env < rule-level vunit_test(env = ...). | Dictionary: String -> String | optional | {} |
| vcom | The vcom VHDL compiler binary. | Label | required | |
| vlib | The vlib library manager binary. | Label | required | |
| vlog | The vlog Verilog/SystemVerilog compiler binary. | Label | required | |
| vsim | The vsim simulator binary. | Label | required |